Semiconductor device and methods of forming the same

A semiconductor device comprising:

• a first device comprising:
• a first protrusion protruding over a substrate;
• a first nanostructure comprising a first semiconductor material and disposed over the first protrusion;
• a first epitaxial extension region disposed on a first sidewall of the first nanostructure;
• a first gate structure comprising a first lower portion between the first nanostructure and the first protrusion;
• a first insulating spacer disposed on a second sidewall of the first lower portion of the first gate structure, wherein the first epitaxial extension region overlaps the first insulating spacer;
• and
• a first source/drain region disposed adjacent to the first protrusion and the first sidewall of the first nanostructure, wherein the first source/drain region comprises a first continuous semiconductor layer disposed on side surfaces of the first epitaxial extension region and the first insulating spacer, wherein the first epitaxial extension region and the first continuous semiconductor layer comprise a second semiconductor material, and the first continuous semiconductor layer has a higher concentration of the second semiconductor material than the first epitaxial extension region.

A method for forming a semiconductor device, the method comprising:

• forming a first semiconductor layer and a second semiconductor layer over a substrate, wherein the first semiconductor layer and the second semiconductor layer comprise a first semiconductor material;
• forming a dummy gate structure over the first semiconductor layer;
• forming a first gate spacer and a second gate spacer interposing the dummy gate structure in a first direction;
• anisotropically etching the first semiconductor layer and the second semiconductor layer using the dummy gate structure, the first gate spacer, and the second gate spacer as masks to form a first nanostructure and a second nanostructure, respectively;
• laterally recessing the first nanostructure and the second nanostructure;
• after the laterally recessing, forming a first epitaxial extension region and a second epitaxial extension region interposing the first nanostructure and a third epitaxial extension region and a fourth epitaxial extension region interposing the second nanostructure, wherein the first epitaxial extension region and third epitaxial extension region overlap the first gate spacer in a plan view, and the second epitaxial extension region and the fourth epitaxial extension region overlap the second gate spacer in the plan view, wherein the first epitaxial extension region is separated from the third epitaxial extension region, and the second epitaxial extension region is separated from the fourth epitaxial extension region, wherein each of the first epitaxial extension region, the second epitaxial extension region, the third epitaxial extension region, and the fourth epitaxial extension region comprises a second semiconductor material different from the first semiconductor material;
• and
• forming a first source/drain region adjacent to the first epitaxial extension region and the third epitaxial extension region and a second source/drain region adjacent to the second epitaxial extension region and the fourth epitaxial extension region, wherein the first source/drain region comprises a first continuous semiconductor layer connecting to the first epitaxial extension region and the third epitaxial extension region, and the second epitaxial extension region comprises a second continuous semiconductor layer connecting to the second epitaxial extension region and the fourth epitaxial extension region, wherein each of the first continuous semiconductor layer and the second continuous semiconductor layer comprises the second semiconductor material.