US 2026/0101573 A1Published application

Semiconductor device and method of manufacturing semiconductor device

AssigneeFuji Electric Co., Ltd.

InventorNaoki KUNESHITA

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Abstract

A semiconductor device, including: a semiconductor substrate; a first semiconductor layer provided at a first surface of the semiconductor substrate; a plurality of first semiconductor regions selectively provided at a first surface of the first semiconductor layer; a plurality of trenches penetrating through the first semiconductor regions and the first semiconductor layer, and reaching the semiconductor substrate; a plurality of gate insulating films provided in the plurality of trenches, respectively; a plurality of gate electrodes provided in the plurality of trenches via the gate insulating films, respectively; an interlayer insulating film provided on the gate electrodes; a first electrode provided on the plurality of first semiconductor regions and the first semiconductor layer; a second electrode provided at a second surface of the semiconductor substrate; and a plurality of tetra ethoxy silane (TEOS) or spin-on-glass (SOG) films embedded in the plurality of gate electrodes in the plurality of trenches, respectively.

Claims7

Dependent claims

A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first surface and a second surface opposite to each other;
a first semiconductor layer of a second conductivity type, provided at the first surface of the semiconductor substrate, the first semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the first semiconductor layer facing the semiconductor substrate;
a plurality of first semiconductor regions of the first conductivity type, selectively provided in the first semiconductor layer, at the first surface of the first semiconductor layer;
a plurality of trenches penetrating through the plurality of first semiconductor regions and the first semiconductor layer and reaching the semiconductor substrate;
a plurality of gate insulating films provided in the plurality of trenches, respectively;
a plurality of gate electrodes provided in the plurality of trenches via the plurality of gate insulating films, respectively;
an interlayer insulating film provided on the plurality of gate electrodes;
a first electrode provided on surfaces of the plurality of first semiconductor regions and the first surface of the first semiconductor layer;
a second electrode provided at the second surface of the semiconductor substrate;
and
a plurality of tetra ethoxy silane (TEOS) films or spin-on-glass (SOG) films embedded in the plurality of gate electrodes in the plurality of trenches, respectively.

8 more elements

A method of manufacturing a semiconductor device, the method comprising:

preparing a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first surface and a second surface opposite to each other;
as a first process, forming a first semiconductor layer of a second conductivity type, at the first surface of the semiconductor substrate, the first semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the first semiconductor layer facing the semiconductor substrate;
as a second process, selectively forming a plurality of first semiconductor regions of the first conductivity type, in the first semiconductor layer, at the first surface of the first semiconductor layer;
as a third process, forming a plurality of trenches penetrating through the plurality of first semiconductor regions and the first semiconductor layer and reaching the semiconductor substrate;
as a fourth process, forming an insulating film along inner walls of the plurality of trenches;
as a fifth process, embedding a polysilicon film so as to form a slit in each of the plurality of trenches;
as a sixth process, etching back the polysilicon film so as to leave a portion thereof in each of the plurality of trenches, thereby forming a gate electrode in each of the plurality of trenches;
as a seventh process, removing portions of the insulating film on surfaces of the plurality of first semiconductor regions and the first surface of the first semiconductor layer so as to leave a portion of the insulating film in each of the plurality of trenches, thereby forming a gate insulating film in each of the plurality of trenches;
as an eighth process, performing a high-temperature heat treatment to the semiconductor substrate;
as a ninth process, embedding a tetra ethoxy silane (TEOS) film in the slit in each of the plurality of trenches;
as a tenth process, forming an interlayer insulating film covering the gate electrode in each of the plurality of trenches;
as an eleventh process, forming a first electrode at the surfaces of the plurality of first semiconductor regions and the first surface of the first semiconductor layer;
and
as a twelfth process, forming a second electrode at the second surface of the semiconductor substrate.

11 more elements

A method of manufacturing a semiconductor device, the comprising:

preparing a semiconductor substrate of a first conductivity type, the semiconductor substrate having a first surface and a second surface opposite to each other;
as a first process, forming a first semiconductor layer of a second conductivity type, at the first surface of the semiconductor substrate, the first semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the first semiconductor layer facing the semiconductor substrate;
as a second process, selectively forming a plurality of first semiconductor regions of the first conductivity type in the first semiconductor layer, at the first surface of the first semiconductor layer;
as a third process, forming a plurality of trenches penetrating through the plurality of first semiconductor regions and the first semiconductor layer and reaching the semiconductor substrate;
as a fourth process, forming an insulating film along an inner wall of each of the plurality of trenches;
as a fifth process, embedding a polysilicon film so as to form a slit in each of the plurality of trenches;
as a sixth process, depositing a spin-on-glass (SOG) film to be embedded in the slit in each of the plurality of trenches;
as a seventh process, removing portions of the SOG film and the insulating film on surfaces of the plurality of first semiconductor regions and the first surface of the first semiconductor layer, so as to leave a portion in each of the plurality of trenches, thereby forming a gate insulating film;
as an eighth process, performing a high-temperature heat treatment to the semiconductor substrate;
as a ninth process, forming an interlayer insulating film covering the gate electrode in each of the plurality of trenches;
as a tenth process, forming a first electrode on the surfaces of the plurality of first semiconductor regions and the first surface of the first semiconductor layer;
and
as an eleventh process, forming a second electrode at the second surface of the semiconductor substrate.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/403,709Filed 28 Nov 2025
Priority: JP 2023-21173715 Dec 2023
Published: 9 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 84/161
Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode: iGBT having built-in components
H10D 8/045
Manufacture or treatment: of PN junction diodes
H10D 8/422
Diodes: pN diodes having the PN junctions in mesas
H10D 12/038
Of vertical IGBTs: having a recessed gate, e.g. trench-gate IGBTs

Family

Application19/403,709Continuation
US 2026/0101573 A1This patent

From the US filing history. Foreign family members aren’t listed.

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