Dipole doping for cfets with reduced loading

A method comprising:

• forming a lower semiconductor nanostructure and an upper semiconductor nanostructure overlapping the lower semiconductor nanostructure;
• forming an upper gate dielectric and a lower gate dielectric on the lower semiconductor nanostructure and the upper semiconductor nanostructure, respectively;
• depositing a first dipole film on the upper gate dielectric and the lower gate dielectric;
• dispensing a directed self-assembly material to embed the first dipole film;
• annealing the directed self-assembly material to form dummy filling-regions, wherein the dummy filling-regions comprise a first plurality of layers and a second plurality of layers located alternatingly;
• recessing the dummy filling-regions to reveal an upper portion of the first dipole film, wherein the upper portion is on the upper gate dielectric;
• etching the upper portion of the first dipole film;
• and
• performing a first annealing process to drive a first dipole dopant in a lower portion of the first dipole film into the lower gate dielectric.

A method comprising:

• forming a lower semiconductor nanostructure and an upper semiconductor nanostructure overlapping the lower semiconductor nanostructure;
• dispensing poly(styrene)-block-poly(methyl methacrylate) (PS-b-PMMA) to cover the lower semiconductor nanostructure and the upper semiconductor nanostructure;
• annealing the PS-b-PMMA to form a plurality of poly(styrene) (PS) layers and a plurality of poly(methyl methacrylate) (PMMA) layers that are located alternatingly;
• using the plurality of PS layers and the plurality of PMMA layers as a mask to form a dipole film, wherein the dipole film encircles a first one of the lower semiconductor nanostructure and the upper semiconductor nanostructure;
• and
• driving a first dipole dopant in the dipole film into a gate dielectric on the first one of the lower semiconductor nanostructure and the upper semiconductor nanostructure.