US 2026/0101562 A1 · TRANSISTOR, INVERTER AND MANUFACTURING METHOD OF THE SAME, AND MEMORY UNIT

Abstract

A transistor, an inverter, a manufacturing method of an inverter and a memory unit are provided. The transistor including a substrate, a stacked structure, and a gate structure. The stacked structure is disposed on the substrate and includes a drain electrode, a source electrode, a semiconductor layer, a first buffer layer, and a second buffer layer. The gate structure includes a gate electrode and a gate dielectric layer. By forming the doped region in the buffer layer to dispose the channel region contact between the source electrode and the drain electrode, the channel layer having the vertical structure is formed, and thereby the vertical transistor having a novel structure is formed. By stacking two transistors on the substrate and allowing the two transistors to share the gate structure, the inverter can have the three-dimensional structure, and the area of the inverter can be reduced to have a relatively small dimension.

Claims20

Dependent claims

A transistor, comprising:

a substrate;
a stacked structure disposed on the substrate, comprising:
a drain electrode;
a source electrode disposed on the drain electrode;
a semiconductor layer disposed between the drain electrode and the source electrode;
a first buffer layer disposed between the drain electrode and the semiconductor layer;
and
a second buffer layer disposed between the source electrode and the semiconductor layer;
and
a gate structure disposed on the substrate, wherein the gate structure extends in a top-down direction of the substrate and penetrates the stacked structure, and the gate structure comprises:
a gate electrode;
and
a gate dielectric layer disposed between the gate electrode and the stacked structure.

10 more elements

An inverter, comprising:

a substrate;
a stacked structure disposed on the substrate and comprising a first stacked structure and a second stacked structure disposed on the first stacked structure, wherein the first stacked structure comprises:
a first source electrode;
a first drain electrode disposed on the first source electrode;
a first semiconductor layer disposed between the first source electrode and the first drain electrode;
a first buffer layer disposed between the first source electrode and the first semiconductor layer;
and
a second buffer layer disposed between the first drain electrode and the first semiconductor layer,
wherein the second stacked structure comprises:
a second drain electrode;
a second source electrode disposed on the second drain electrode;
and
an insulating layer disposed between the second drain electrode and the second source electrode;
a gate structure disposed on the substrate, wherein the gate structure extends in a top-down direction of the substrate and penetrates the stacked structure, and the gate structure comprises:
a gate electrode;
and
a gate dielectric layer disposed between the gate electrode and the stacked structure;
and
a second semiconductor layer disposed between the gate structure and the second stacked structure, wherein the second semiconductor layer is in contact with the second source electrode and the second drain electrode.

16 more elements

A manufacturing method of an inverter, comprising:

forming a first stacked structure material layer comprising a first semiconductor layer;
forming a second stacked structure material layer on the first stacked structure material layer;
forming a first contact window and a second contact window, wherein the first contact window is electrically connected to a first source electrode in the first stacked structure material layer and a second source electrode in the second stacked structure material layer, and the second contact window is electrically connected to a first drain electrode in the first stacked structure material layer and a second drain electrode in the second stacked structure material layer;
removing a portion of the second stacked structure material layer to form a first trench, and forming a second semiconductor layer in the first trench, wherein the second semiconductor layer is in contact with the second source electrode and the second drain electrode;
removing a portion of the first stacked structure material layer through the first trench to form a second trench, wherein a width of the second trench is smaller than a width of the first trench;
and
forming a gate structure filling the first trench and the second trench.

4 more elements

Dependencies are inferred from the claim text.

Transistor, inverter and manufacturing method of the same, and memory unit

Life of this patent

Transistor, inverter and manufacturing method of the same, and memory unit

Life of this patent

Abstract

Claims20