Forming seams with desirable dimensions in isolation regions

A method comprising:

• forming dielectric isolation regions in a semiconductor substrate;
• forming a protruding semiconductor fin protruding higher than the dielectric isolation regions;
• forming gate spacers over the protruding semiconductor fin;
• forming a fin isolation region between the gate spacers, wherein the fin isolation region penetrates through the protruding semiconductor fin and comprises a seam therein, with the seam extending from a higher level at least to a lower level, wherein:
• the higher level is coplanar with top surfaces of the gate spacers;
• and
• the lower level is at a same level as a top surface of the dielectric isolation regions;
• and
• forming a first source/drain region and a second source/drain region, wherein the first source/drain region and the second source/drain region are on opposite sides of the fin isolation region.

A method comprising:

• forming dielectric isolation regions in a semiconductor substrate;
• forming a protruding semiconductor fin protruding higher than the dielectric isolation regions;
• forming a dummy gate stack over a top surface and on sidewalls of the protruding semiconductor fin;
• forming a first gate spacer and a second gate spacer opposing to each other, wherein sidewalls of the first gate spacer and the second gate spacer contact sidewalls of the dummy gate stack to form vertical interfaces;
• etching the dummy gate stack and semiconductor materials overlapped by the dummy gate stack to form a trench;
• filling the trench with a dielectric material, wherein the dielectric material comprises a seam therein, and wherein the seam is fully sealed in the dielectric material;
• and
• performing a planarization process on the dielectric material to form a fin isolation region between and contacting the first gate spacer and the second gate spacer, wherein the seam is exposed to an external environment as a result of the planarization process.