Transistor structure having increased source/drain current and method of manufacturing thereof

A method of forming a semiconductor device, comprising:

• forming a fin structure comprising an alternating layer stack comprising first semiconductor layers and second semiconductor layers stacked along a thickness direction;
• patterning the fin structure to form source/drain regions separated from one another along a length direction of the fin structure;
• removing the first semiconductor layers;
• forming a dielectric interposer layer within spaces between the second semiconductor layers previously occupied by the first semiconductor layers;
• forming source/drain epitaxial layers in the source/drain regions;
• and
• performing an annealing operation after forming the source/drain epitaxial layers and the dielectric interposer layer.

The method of claim further comprising:

• removing the dielectric interposer layer between the second semiconductor layers such that the second semiconductor layers form stacked channel regions extending between adjacent source/drain epitaxial layers;
• forming a gate dielectric layer around each of the stacked channel regions;
• and
• forming a gate structure that surrounds each of the stacked channel regions.

A semiconductor device, comprising:

• a fin structure comprising a plurality of semiconductor layers stacked along a thickness direction and configured as stacked channel regions;
• a gate structure formed around each of the stacked channel regions;
• and
• source/drain epitaxial layers formed on opposite ends of the stacked channel regions along a length direction of the fin structure,
• wherein:
• each of the stacked channel regions comprises a thickness greater than 5 nm;
• and
• each of the stacked channel regions comprises a thickness variation that is less than 1 nm.