Transistor structure of transistors with shared gate

A method of forming a transistor structure, said method comprising:

• forming an upper transistor and a lower transistor, said upper transistor comprising a gate, wherein the gate comprises a lower portion and an upper portion, wherein the lower transistor comprises the lower portion of the gate and does not comprise the upper portion of the gate, wherein the upper transistor is a nanosheet (NS) transistor, and wherein the lower transistor is a two-dimensional (2D) channel transistor.

A transistor structure, comprising:

• an upper transistor comprising a gate, wherein the gate comprises a lower portion and an upper portion, and wherein the upper transistor is a nanosheet (NS) transistor;
• and
• a lower transistor comprising the lower portion of the gate and not comprising the upper portion of the gate, wherein the lower transistor comprises a first backside contact and does not comprise any other backside contact, and wherein the lower transistor is a two-dimensional (2D) channel transistor.