US 2026/0101528 A1 · MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

A memory device and a manufacturing method thereof are provided. The memory device includes: an access transistor; and a capacitor contact structure configured to connect a source/drain of the access transistor to an overlying storage capacitor, and including: a bottom contact structure; and a top contact structure disposed above the bottom contact structure and including a barrier layer and a conductive filler material connected to the bottom contact structure via the barrier layer. The barrier layer is extended along a bottom portion and two opposite sidewalls of the conductive filler material. A lower portion of the conductive filler material is filled in a recess defined by the barrier layer, and an upper portion of the conductive filler material is higher than a topmost end of the barrier layer and has a greater width relative to the lower portion of the conductive filler material.

Claims19

Dependent claims

A memory device, comprising:

an access transistor;
a capacitive contact structure configured to connect a drain/source of the access transistor to an overlying storage capacitor, and comprising:
a bottom contact structure;
and
a top contact structure disposed above the bottom contact structure and comprising a barrier layer and a conductor filler material connected to the bottom contact structure via the barrier layer, wherein the barrier layer is extended along a bottom surface and two opposite sidewalls of the conductor filler material, a lower portion of the conductor filler material is filled in a recess defined by the barrier layer, and an upper portion of the conductor filler material is higher than a topmost end of the barrier layer and has a greater width relative to the lower portion;
and
a bit line stack structure adjacent to the capacitive contact structure and having a bit line connected to another drain/source of the access transistor.

4 more elements

A method of forming a memory device, comprising:

forming a plurality of access transistors in a substrate;
forming a bit line stack structure on the substrate, wherein the bit line stack structure crosses over a plurality in the plurality of access transistors;
and
forming a plurality of capacitive contact structures on the substrate along two sides of the bit line stack structure, wherein the plurality of capacitive contact structures respectively comprise:
a bottom contact structure;
and
a top contact structure disposed above the bottom contact structure and comprising a barrier layer and a conductor filler material connected to the bottom contact structure via the barrier layer, wherein the barrier layer is extended along a bottom surface and two opposite sidewalls of the conductor filler material, a lower portion of the conductor filler material is filled in a recess defined by the barrier layer, and an upper portion of the conductor filler material is higher than a topmost end of the barrier layer and has a greater width relative to the lower portion.

4 more elements

Dependencies are inferred from the claim text.

Memory device and manufacturing method thereof

Life of this patent

Memory device and manufacturing method thereof

Life of this patent

Abstract

Claims19