Heterogeneous memory stack

Abstract

A stacked memory device includes a first memory die and a second memory die. The first memory die has multi-layer structure and each of a plurality of layers of the first memory die includes at least a memory cell region and a through-silicon-via (TSV) region. The first memory die is electrically connected to an integrated circuit device through a plurality of vertical interconnects within the TSV region. The second memory die is disposed between the first memory die and the integrated circuit device. The second memory die has single layer structure, and the second memory die includes at least a memory cell region and a TSV region. The second memory die is electrically connected to the integrated circuit device through surface bonding.

Dependencies are inferred from the claim text.