Method of integration of non-volatile memory device having vertical channels formation into cmos flow

An embedded semiconductor device, comprising:

• a non-volatile memory (NVM) array disposed in a core region of a substrate, including:
• a plurality of source lines (SLs) extending in a first direction, wherein adjacent SLs are insulated by shallow trench isolations (STIs);
• NVM transistors formed overlying the plurality of SLs, each NVM transistor comprising a lower source/drain (S/D) junction, a vertical channel surrounded by a memory film stack and a metal gate layer, and an upper S/D junction overlying the vertical channel;
• a plurality of word lines (WLs) coupling to the metal gate layers of the NVM transistors and extending in a second direction;
• and
• a plurality of bit lines (BLs) overlying the upper S/D junctions and the metal gates of the NVM transistors, wherein the BLs are coupled to the upper S/D junctions of at least one NVM transistors and extend in the first direction and
• at least one logic transistor disposed in a periphery region of the substrate, each logic transistor including a gate dielectric layer overlying a horizontal channel, a gate layer, and a height-enhancement (HE) layer.

A semiconductor device, comprising:

• a plurality of non-volatile memory (NVM) transistors arranged in rows and columns formed in a substrate, wherein each NVM transistor comprises a lower source/drain (S/D) junction, a vertical channel surrounded by a memory film stack and a metal gate layer, and an upper S/D junction overlying the vertical channel;
• a plurality of logic transistors formed in the substrate, each logic transistor including a gate dielectric layer overlying a horizontal channel, a gate layer, and a height-enhancement (HE) layer;
• a plurality of word lines (WLs), each coupling NVM transistors of a same row, wherein metal gate layers of the NVM transistors of the row form a portion of the WLs;
• a plurality of source lines (SLs), each coupling NVM transistors of two adjacent columns, wherein lower S/D junction of the NVM transistors of the two adjacent columns form a portion of the SLs;
• and
• a plurality of bit lines (BLs), each coupling NVM transistors of at least one column via a plurality of BL connects.