US 2026/0101503 A1 · DUAL-ANTIFUSE DEVICES AND MEMORY STRUCTURES INCLUDING DUAL-ANTIFUSE DEVICES

Abstract

Disclosed is a dual-antifuse (DAF) device with two electrically isolated antifuses. The DAF device includes a gate structure including a dielectric layer lining a recess in a semiconductor layer between first and second conductive regions and a conductor layer on the dielectric layer. A gate cut isolation structure extends through the conductor layer, dividing the conductor layer into first and second conductor sections. As a result, the device includes a first antifuse (i.e., the first conductor section, the first conductive region, and the dielectric layer therebetween) and a second antifuse (i.e., a second conductor section, the second conductive region, and the dielectric layer therebetween), which is isolated from the first antifuse. Thus, the two antifuses are independently programable. Also disclosed herein are memory structure embodiments, which include DAF devices (either with or without electrically isolated antifuses) integrated into the cells of an array and which are configured for improved reliability.

Claims20

Dependent claims

A structure comprising:

a semiconductor layer having a top surface and a recess in the top surface;
a trench isolation structure in the semiconductor layer below the recess;
and
a gate structure on the trench isolation structure, wherein the gate structure includes a dielectric layer lining the recess and, on the dielectric layer, a first conductor section and a second conductor section positioned laterally adjacent and isolated from the first conductor section.

1 more element

A structure comprising:

an array of cells arranged in rows and columns;
wordlines for the rows, respectively;
bitlines for the columns, respectively;
and
multiple dual-antifuse devices,
wherein each cell includes:
a pass gate transistor;
and one antifuse of a dual-antifuse device of the dual-antifuse devices,
wherein, within each cell, the one antifuse is connected between a wordline for a row and the pass gate transistor, and
wherein, within each cell, the pass gate transistor is connected between the one antifuse and a bitline for a column and further has a gate connected to the wordline for the row.

7 more elements

A structure comprising:

an array of cells arranged in rows and columns;
wordlines for the rows, respectively;
bitlines for the columns, respectively;
and
multiple dual-antifuse devices,
wherein each cell includes:
a dual-antifuse device of the multiple dual-antifuse devices;
and a pass gate transistor,
wherein, within each cell, the dual-antifuse device includes a first antifuse connected between a wordline for a row and the pass gate transistor and a second antifuse with a first terminal connected to the wordline for the row and a second terminal that is any of floated and connected to a common node, and
wherein, within each cell, the pass gate transistor is connected between the first antifuse and a bitline for a column and further has a gate connected to the wordline for the row.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/910,268Filed 9 Oct 2024

Published

9 Apr 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 20/25
Programmable ROM [PROM] devices comprising field-effect components: one-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
G11C 17/18
In which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of…
H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Dual-antifuse devices and memory structures including dual-antifuse devices

Life of this patent

Dual-antifuse devices and memory structures including dual-antifuse devices

Life of this patent

Abstract

Claims20