Semiconductor memory device and method for manufacturing the same

A semiconductor memory device comprising:

• a substrate including a first area and a second area arranged along a first direction;
• an active pattern disposed in the first area and including a first portion and a second portion;
• a gate electrode extending in a second direction intersecting the first direction, the gate electrode crossing between the first portion and the second portion;
• a conductive pattern disposed on the substrate and connected to the first portion, the conductive pattern extending in the first direction, and having an end on the second area;
• a spacer structure disposed on and extending along a side surface of the conductive pattern;
• a buried contact disposed on the spacer structure on the first area, the buried contact connecting to the second portion;
• a capacitor structure connected to the buried contact;
• and
• an edge insulating film disposed on the spacer structure on the second area,
• wherein a portion of the spacer structure is interposed between the substrate and the edge insulating film.

A semiconductor memory device comprising:

• a substrate including a cell area and a peripheral area around the cell area, wherein the cell area comprises a first area and a second area interposed between the first area and the peripheral area in a first direction;
• an active pattern disposed in the first area and including a first portion and a second portion;
• a gate electrode extending in a second direction intersecting the first direction, the gate electrode crossing between the first portion and the second portion;
• a first conductive line disposed on the substrate and connected to the first portion, the first conductive line extending in the first direction;
• a second conductive line disposed on the substrate and extending in the first direction, the second conductive line being spaced apart from the first conductive line in the second direction;
• a buried contact disposed between the first conductive line and the second conductive line and connecting the second portion;
• a capacitor structure connected to the buried contact;
• and
• an edge insulating film disposed on the second area,
• wherein the first conductive line comprises:
• a first line portion disposed on the first area;
• and
• a first edge portion disposed on the second area and having an end of the first conductive line,
• wherein the second conductive line comprises:
• a second line portion disposed on the first area;
• and
• a second edge portion disposed on the second area and having an end of the second conductive line, the second edge portion protruding beyond the first edge portion toward the peripheral area,
• wherein the edge insulating film comprises:
• a first filling portion interposed between the first edge portion and the second edge portion in the second direction;
• and
• a second filling portion overlapping the first edge portion in the first direction and overlapping the second edge portion in the second direction.