Integrated circuit devices

An integrated circuit device, comprising:

• a substrate;
• a bit line extending on the substrate in a first direction parallel to an upper surface of the substrate;
• a source region on the bit line and comprising p-type impurities;
• a channel layer on the source region, extending in a second direction perpendicular to the upper surface of the substrate, and comprising a first sidewall;
• a gate insulating layer on the first sidewall of the channel layer and on an upper surface of the source region;
• a floating metal layer comprising a first floating metal layer and a second floating metal layer, wherein the first floating metal layer is on the upper surface of the source region, and the second floating metal layer is on the first sidewall of the channel layer, wherein the gate insulating layer is between the channel layer and the floating metal layer and between the source region and the floating metal layer;
• a word line on an upper surface of the first floating metal layer;
• a ferroelectric layer between the first floating metal layer and the word line and between the second floating metal layer and the word line;
• a drain region on an upper surface of the channel layer and comprising p-type impurities;
• and
• a source line electrically connected to the drain region and extending in the first direction,
• wherein a thickness of the first floating metal layer in the second direction is greater than a thickness of the second floating metal layer in the first direction, and
• wherein an area of contact between the channel layer and the gate insulating layer is greater than an area of contact between the ferroelectric layer and the floating metal layer.

An integrated circuit device, comprising:

• a substrate;
• a bit line extending on the substrate in a first direction parallel to an upper surface of the substrate;
• a mold insulating layer on the substrate and on the bit line and comprising a hole therein;
• a source region in the hole of the mold insulating layer, on an upper surface of the bit line, and comprising p-type impurities;
• a channel layer in the hole of the mold insulating layer and extending on the source region in a second direction perpendicular to the upper surface of the substrate, the channel layer comprising polysilicon, silicon germanium, an oxide semiconductor material, or a two-dimensional material, and having a first sidewall and a second sidewall opposite each other, wherein the second sidewall is in contact with the mold insulating layer;
• a gate insulating layer and a floating metal layer in the hole of the mold insulating layer, the gate insulating layer extending in the second direction on the first sidewall of the channel layer and in the first direction on an upper surface of the source region;
• a ferroelectric layer in the hole of the mold insulating layer and conformally extending on a sidewall of a vertical extension portion of the floating metal layer and an upper surface of a horizontal extension portion of the floating metal layer;
• a word line in the hole of the mold insulating layer and on the ferroelectric layer;
• a drain region in the hole of the mold insulating layer, on an upper surface of the channel layer, and comprising p-type impurities;
• and
• a source line electrically connected to the drain region and extending in the first direction,
• wherein a thickness of the horizontal extension portion of the floating metal layer in the second direction is greater than a thickness of the vertical extension portion of the floating metal layer in the first direction,
• wherein an area of contact between the channel layer and the gate insulating layer is greater than an area of contact between the ferroelectric layer and the floating metal layer, and
• wherein a thickness of the ferroelectric layer is not greater than 20 nm.