Semiconductor structure and manufacturing method thereof

A method, comprising:

• forming a first static random access memory (SRAM) cell in a device layer, wherein the first SRAM cell each comprises a first pull-up transistor and a first pull-down transistor;
• forming a second SRAM cell in the device layer, wherein the second SRAM cell comprises a second pull-up transistor and a second pull-down transistor;
• forming a match cell in the device layer, wherein the match cell comprises a first gate data transistor and a second gate data transistor, a gate of the first gate data transistor is electrically coupled to a gate of the first pull-up transistor and the first pull-down transistor, and a gate of the second gate data transistor is electrically coupled to a gate of the second pull-up transistor and the second pull-down transistor;
• forming a first back-side contact extending over a source/drain region of the first pull-down transistor of the first SRAM cell;
• and
• forming a first power supply voltage line over the first back-side contact, the first power supply voltage line being electrically coupled to the source/drain region of the first pull-down transistor through the first back-side contact.

A semiconductor structure, comprising:

• a backside dielectric layer;
• a first transistor cell over the backside dielectric layer, the first transistor cell comprising a first channel layer being of a first conductivity type and a second channel layer being of a second conductivity type, wherein from a top view, the first channel layer has a first width along a lengthwise direction of the first transistor cell, the second channel layer has a second width along the lengthwise direction of the first transistor cell, and the second width is different from the first width;
• a second transistor cell over the backside dielectric layer;
• a cell boundary region over the backside dielectric layer and coupling to the first and the second transistors cells, the cell boundary region comprising a first epitaxial source/drain structure and a second epitaxial source/drain structure separated from the first epitaxial source/drain structure by an isolation layer and located at an edge of the cell boundary region from a cross-sectional view, the first epitaxial source/drain structure being of the first conductivity type and connecting the first channel layer, and the second epitaxial source/drain structure being of the second conductivity type and connecting the second channel layer;
• a backside conductive layer underlying the backside dielectric layer and coupling to a back-side of the first epitaxial source/drain structure;
• and
• a front-side metal routing layer coupling to a front-side of the second epitaxial source/drain structure.