Cfet sram device, layout, and method

A method of manufacturing an integrated circuit (IC) device, the method comprising:

• constructing, on a front side of a substrate, first through fourth complementary field-effect transistors (CFETs) configured as a static random-access memory (SRAM) device, the constructing the first through fourth CFETs comprising:
• constructing the first CFET by forming a first pull-down transistor at a first elevation along a first direction and a first pull-up transistor at a second elevation along the first direction;
• constructing the second CFET by forming a first pass-gate transistor at the first elevation and aligned with the first pull-down transistor in a second direction perpendicular to the first direction;
• constructing the third CFET by forming a second pass-gate transistor at the first elevation and aligned with the first pull-down transistor in a third direction perpendicular to the first and second directions;
• and
• constructing the fourth CFET by forming a second pull-down transistor at the first elevation, aligned with the first pass-gate transistor in the third direction, and aligned with the second pass-gate transistor in the second direction, and a second pull-up transistor at the second elevation;
• forming a first bit line extending in the third direction at a third elevation along the first direction and electrically connected to a source/drain (S/D) structure of the first pass-gate transistor;
• forming a second bit line extending in the third direction at the third elevation and electrically connected to a S/D structure of the second pass-gate transistor;
• and
• forming a first reference voltage line extending between the first and second bit lines at the third elevation and electrically connected to a S/D structure of the first pull-down transistor.

A method of generating an integrated circuit (IC) layout diagram, the method comprising:

• arranging a bit line pair across a static random-access memory (SRAM) cell comprising first through fourth complementary field-effect transistors (CFETs), wherein
• the first CFET comprises a first pull-down transistor stacked with a first pull-up transistor,
• the second CFET comprises a first pass-gate transistor aligned with the first pull-down transistor in a first direction,
• the third CFET comprises a second pass-gate transistor aligned with the first pull-down transistor in a second direction perpendicular to the first direction,
• the fourth CFET comprises a second pull-down transistor stacked with a second pull-up transistor, aligned with the first pass-gate transistor in the second direction, and aligned with the second pass-gate transistor in the first direction, and
• the bit lines of the bit line pair are electrically connected to source/drain (S/D) regions of the first and second pass-gate transistors;
• arranging a reference voltage line between the bit lines of the bit line pair and electrically connected to a S/D region of the first pull-down transistor;
• and
• storing the IC layout diagram comprising the SRAM cell comprising the bit line pair and the reference voltage line in a storage device.