Semiconductor package

A semiconductor package comprising:

• a substrate comprising a first surface and a second surface that are opposite to each other in a first direction;
• a first semiconductor chip disposed on the second surface, and comprising a third surface facing the second surface and a fourth surface opposite to the third surface in the first direction;
• a second semiconductor chip disposed on the second surface, wherein the second semiconductor chip is configured to operate based on a power supply voltage, and comprises a fifth surface and a sixth surface that are opposite to each other in the first direction, the fifth surface faces the third surface and the sixth surface faces the second surface;
• a power management integrated circuit (PMIC) on the second surface, wherein the PMIC is configured to generate the power supply voltage, provide the power supply voltage to the second semiconductor chip, and comprises a seventh surface facing the fifth surface and an eighth surface opposite to the seventh surface in the first direction;
• and
• first connecting terminals provided on the fifth surface,
• wherein a first plurality of the first connecting terminals are provided on the third surface, and
• wherein a second plurality of the first connecting terminals are provided on the seventh surface.

A semiconductor package comprising:

• a substrate comprising a first surface and a second surface that are opposite to each other in a first direction;
• a first semiconductor chip on the second surface, and comprising a third surface facing the second surface and a fourth surface opposite to the third surface in the first direction;
• a second semiconductor chip comprising a fifth surface and a sixth surface that are opposite to each other in the first direction, wherein the second semiconductor chip is configured to operate based on a power supply voltage;
• and
• a power management integrated circuit (PMIC) on the second surface, wherein the PMIC is configured to generate the power supply voltage, provide the power supply voltage to the second semiconductor chip, and comprises a seventh surface facing the second surface and an eighth surface opposite to the seventh surface in the first direction,
• wherein at least a first portion of the second semiconductor chip overlaps the first semiconductor chip along the first direction, and
• wherein at least a second portion of the second semiconductor chip overlaps the PMIC along the first direction.