Iterative detection and decoding (idd) circuit for calculating low-power consumption log-likelihood ratio, operation method of the idd circuit, and modem chip

An operation method of an iterative detection and decoding (IDD) circuit, the operation method comprising:

• receiving a signal including a symbol;
• and
• performing N iterative operations, where N is an integer of 2 or more,
• wherein a first iterative operation from among the N iterative operations comprises:
• generating a first log-likelihood ratio based on the symbol by using a linear detection method;
• performing a first decoding operation based on the first log-likelihood ratio;
• terminating the N iterative operations, when the first decoding operation is successful;
• and
• generating a post-log-likelihood ratio based on the first log-likelihood ratio, when the first decoding operation fails, and
• an N-th iterative operation from among the N iterative operations comprises:
• generating a second log-likelihood ratio based on the symbol and the post-log-likelihood ratio by using a nonlinear detection method;
• and
• performing a second decoding operation based on the second log-likelihood ratio.

A modem chip comprising:

• a radio-frequency integrated circuit (RFIC);
• and
• a processor configured to receive, via the RFIC, a reception signal including a symbol,
• wherein the processor is further configured to:
• generate a first log-likelihood ratio based on the symbol by using a linear detection method;
• perform a first decoding operation based on the first log-likelihood ratio;
• generate a post-log-likelihood ratio, when the first decoding operation fails;
• generate a second log-likelihood ratio based on the symbol and the post-log-likelihood ratio by using a nonlinear detection method, when the first decoding operation fails;
• and
• perform a second decoding operation based on the second log-likelihood ratio.