US 2026/0100867 A1 · FEEDFORWARD PHASE CORRECTION

Abstract

A pulse amplitude modulation 4-level (PAM-4) physical layer (PHY) serializer/deserializer (SerDes) receiver is provided. The receiver may include an analog-front-end (AFE) block to receive a transmit signal, an analog-to-digital converter (ADC) block to convert the transmit signal into a digital signal at sampling intervals defined by a sampling clock signal, a clock and data recovery (CDR) circuit to receive the digital signal from the ADC block and extract a recovered clock signal and a recovered data stream, the recovered data stream containing a sequence of symbols with amplitude values corresponding to four levels of PAM-4, a phase integrator (PI) to generate the sampling clock signal for the ADC block based on the recovered clock signal, and a feedforward phase correction (FFPC) block to receive the recovered data stream and generate a receive signal.

Claims19

Dependent claims

A pulse amplitude modulation 4-level (PAM-4) physical layer (PHY) serializer/deserializer (SerDes) receiver comprising:

an analog-front-end (AFE) block to receive a transmit signal;
an analog-to-digital converter (ADC) block to convert the transmit signal into a digital signal at sampling intervals defined by a sampling clock signal;
a clock and data recovery (CDR) circuit to receive the digital signal from the ADC block and extract a recovered clock signal and a recovered data stream, the recovered data stream containing a sequence of symbols with amplitude values corresponding to four levels of PAM-4;
a phase integrator (PI) to generate the sampling clock signal for the ADC block based on the recovered clock signal;
and
a feedforward phase correction (FFPC) block to receive the recovered data stream and generate a receive signal, the FFPC block comprising:
a feed-forward equalization/decision feedback equalization (FFE/DFE) block to equalize the recovered data stream across different receiver paths including a leading path, a nominal path, and a lagging path;
a slicer error computation block to compute one or more slicer errors for the symbols of the sequence of symbols;
and
a receiver path selection block to compute a total slicer error for each receiver path and select the receiver path with the lowest total slicer error.

7 more elements

Dependencies are inferred from the claim text.

Feedforward phase correction

Life of this patent

Feedforward phase correction

Life of this patent

Abstract

Claims19