Duty cycle correction circuit and method for operating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorCHANG-YI LI
Life of this patent
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Abstract
The present disclosure provides an integrated circuit, which includes a master circuit and a slave circuit. The master circuit is configured to receive an input clock signal and generate an intermediate clock signal based on a first half and a second half of a first trimming code. The slave circuit is electrically connected to the master circuit and is configured to receive the intermediate clock signal and generate an output clock signal from the intermediate clock signal based on a first half and a second half of a second trimming code. The first trimming code is complementary to the second trimming code.
Claims20
An integrated circuit, comprising:
- a master circuit, configured to receive an input clock signal and generate an intermediate clock signal based on a first half and a second half of a first trimming code;
- and
- a slave circuit, electrically connected to the master circuit, and configured to receive the intermediate clock signal and generate an output clock signal from the intermediate clock signal based on a first half and a second half of a second trimming code,
- wherein the first trimming code is complementary to the second trimming code.
An integrated circuit, comprising:
- a master circuit, configured to receive an input clock signal and generate an intermediate clock signal based on a first trimming code;
- and
- a slave circuit, electrically connected to the master circuit, and configured to receive the intermediate clock signal and generate an output clock signal from the intermediate clock signal based on a second trimming code complementary to the first trimming code.
A method, comprising:
- providing a master compensation circuit and a slave compensation circuit connected in series;
- utilizing the master compensation circuit to generate an intermediate clock signal from an input clock signal through a first trimming circuit and a second trimming circuit which receive a first half of a first trimming code and a second half of the first trimming code, respectively;
- and
- utilizing the slave compensation circuit to generate an output clock signal from the intermediate clock signal through a third trimming circuit and a fourth trimming circuit which receive a first half of a second trimming code and a second half of the second trimming code, respectively, wherein the second trimming code is complementary to the first trimming code.
Dependencies are inferred from the claim text.