Dynamic high-speed flip flop

An apparatus comprising:

• means for receiving an input signal asserted at a HIGH state of the input signal at a master latch section, and at a slave latch section with a glitch mitigation;
• means for executing a positive clock transition throughout the master latch section and the slave latch section;
• and
• means for transitioning a state (Q) signal from a LOW state to a HIGH state of the state (Q) signal subsequent to the positive clock transition.

A method comprising:

• receiving an input signal asserted at a HIGH state of the input signal at a master latch section, and at a slave latch section with a glitch mitigation;
• executing a positive clock transition throughout the master latch section and the slave latch section;
• and
• transitioning a state (Q) signal from a LOW state to a HIGH state of the state (Q) signal subsequent to the positive clock transition.