Nonvolatile memory device and memory system including the same

A memory system comprising:

• a nonvolatile memory device configured to output a read data;
• and
• a memory controller configured to control the nonvolatile memory device and correct errors in the read data,
• wherein the nonvolatile memory device comprises:
• a plurality of page buffer circuits corresponding to a plurality of memory planes, each of the plurality of page buffer circuits connected to a respective one of the plurality of memory planes through corresponding bit-lines;
• a first group of first-in/first-out (FIFO) registers connected to the plurality of page buffer circuits, respectively;
• a second group of FIFO registers connected to the first group of FIFO registers, respectively;
• a multiplexer configured to select one of a plurality of sub data output from the second group of FIFO registers, in response to a plane selection signal;
• and
• a control circuit configured to control the plurality of page buffer circuits, the first group of FIFO registers and the second group of FIFO registers,
• wherein the control circuit is configured to:
• perform a first read operation, in response to a first read command, wherein the first read operation comprises sensing a first data stored in a first memory plane among the plurality of memory planes through a first page buffer circuit and storing the first sensed data in a corresponding first set of FIFO registers among the first group of FIFO registers and the second group of FIFO registers as a first sub data;
• and
• perform a second read operation, in response to a second read command, wherein the second read operation comprises sensing a second data stored in a second memory plane among the plurality of memory planes through a second page buffer circuit and storing the second sensed data in a corresponding second set of FIFO registers among the first group of FIFO registers and the second group of FIFO registers as a second sub data while performing a first output operation to output the first sub data to the memory controller through the multiplexer and a data input/output circuit in response to a first data output command.

A nonvolatile memory device comprising:

• a memory cell array including a plurality of memory planes;
• a plurality of page buffer circuits corresponding to a plurality of memory planes, each of the plurality of page buffer circuits connected to a respective one of the plurality of memory planes through corresponding bit-lines;
• a first group of first-in/first-out (FIFO) registers connected to the plurality of page buffer circuits, respectively;
• a second group of FIFO registers connected to the first group of FIFO registers, respectively;
• a multiplexer configured to select one of a plurality of sub data output from the second group of FIFO registers, in response to a plane selection signal;
• and
• a control circuit configured to control the plurality of page buffer circuits, the first group of FIFO registers and the second group of FIFO registers,
• wherein the control circuit is configured to:
• perform a first read operation, in response to a first read command, wherein the first read operation comprises sensing a first data stored in a first memory plane among the plurality of memory planes through a first page buffer circuit and storing the first sensed data in a first FIFO register among the first group of FIFO registers and in a second FIFO register among the second group of FIFO registers as a first sub data;
• and
• perform a second read operation, in response to a second read command, wherein the second read operation comprises sensing a second data stored in a second memory plane among the plurality of memory planes through a second page buffer circuit and storing the second sensed data in a third FIFO register among the first group of FIFO registers and in a fourth FIFO register among the second group of FIFO registers as a second sub data while performing a first output operation to output the first sub data to a circuit outside of the nonvolatile memory device through the multiplexer and a data input/output circuit in response to a first data output command,
• wherein the control circuit is configured to perform the first output operation immediately upon receipt of the first data output command.