Dynamic program pulse widths for different sub-blocks in a memory device
AssigneeMicron Technology, Inc.
InventorsYu-Chung Lien, Zhenming Zhou
Life of this patent
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Abstract
A memory device includes a memory array with a plurality of blocks and control logic to initiate a program operation on one or more memory cells in a first sub-block of one of the plurality of blocks of the memory array. The control logic further identifies a categorization of the first sub-block, determines a corresponding program pulse width based on the categorization of the first sub-block, and causes a program voltage pulse having the corresponding program pulse width to be applied to the one or more memory cells during the program operation.
Claims20
A memory device comprising:
- a memory array comprising a plurality of blocks;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- initiating a program operation on one or more memory cells in a first sub-block of one of the plurality of blocks of the memory array;
- identifying a categorization of the first sub-block;
- determining a corresponding program pulse width based on the categorization of the first sub-block;
- and
- causing a program voltage pulse having the corresponding program pulse width to be applied to the one or more memory cells during the program operation.
A method comprising:
- initiating a program operation on one or more memory cells in a first sub-block of one of a plurality of blocks of a memory device;
- identifying a categorization of the first sub-block;
- determining a corresponding program pulse width based on the categorization of the first sub-block;
- and
- causing a program voltage pulse having the corresponding program pulse width to be applied to the one or more memory cells during the program operation.
A memory device comprising:
- a memory array comprising a plurality of blocks;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- initiating a program operation on one or more memory cells in each of a plurality of sub-blocks of one of the plurality of blocks of the memory array;
- identifying respective categorizations of each of the plurality of sub-blocks;
- determining respective program pulse widths for each of the plurality of sub-blocks based on the respective categorizations;
- and
- causing a plurality of program voltage pulses having the respective program pulse widths to be applied to the one or more memory cells during the program operation.
Dependencies are inferred from the claim text.