Semiconductor memory device

A semiconductor memory device comprising:

• a nonvolatile memory cell;
• a first circuit configured to receive first bit data of an input signal based on a first clock signal, and output a first signal based on a result of comparison between a value obtained by subtracting a predetermined coefficient from the first bit data and a value obtained by adding the coefficient to a reference voltage;
• a second circuit configured to receive the first bit data of the input signal based on the first clock signal, and output a second signal based on a result of comparison between a value obtained by adding the coefficient to the first bit data and a value obtained by subtracting the coefficient from the reference voltage;
• a third circuit configured to receive second bit data of the input signal based on a second clock signal obtained by inverting the first clock signal, and output a third signal based on a result of comparison between a value obtained by subtracting the coefficient from the second bit data and a value obtained by adding the coefficient to the reference voltage;
• a fourth circuit configured to receive the second bit data of the input signal based on the second clock signal, and output a fourth signal based on a result of comparison between a value obtained by adding the coefficient to the second bit data and a value obtained by subtracting the coefficient from the reference voltage;
• a first multiplexer configured to output one of the first signal and the second signal as a fifth signal;
• a second multiplexer configured to output one of the third signal and the fourth signal as a sixth signal;
• a fifth circuit configured to receive the fifth signal based on the first clock signal, and output first data based on the fifth signal;
• and
• a sixth circuit configured to receive the sixth signal based on the second clock signal, and output second data based on the sixth signal.