Content addressable memory and semiconductor device

Abstract

A content addressable memory includes a cell array capable of storing a plurality of data entries, a plurality of valid cells provided for each of the data entries and configured to store valid bits indicating valid or invalid of the data entry, an All-invalid detection circuit configured to detect that the plurality of valid bits all indicate invalid, a search unit configured to determine matching or mismatching between the plurality of data entries and search data, and a control unit configured to stop the search unit when the All-invalid detection circuit detects that the valid bits all indicate invalid.

Dependencies are inferred from the claim text.