Sram physical unclonable function with improved bit error rate

A method for authenticating an integrated circuit having a memory array that includes plural memory cells arranged in plural rows and plural columns, each row is formed by a word line and each column is formed by a pair of bit lines, each memory cell including a pair of cross coupled inverters connected between a pair of access transistors, each access transistor is connected to one bit line of the pair of bit lines forming the column, and each access transistor has a gate connected to the word line forming the row;

• a decoder configured to output a binary value for selecting each of the memory cells based on the pair of bit lines and the word line to which the memory cell is connected;
• a sense amplifier connected between the pair of bit lines forming a column of the plural columns;
• and a pre-charge circuit connected to a primary voltage and to the pair of bit lines in each column, the method comprising:
• writing a pattern of bits into the plural memory cells the memory array;
• pre-charging, by the pre-charge circuit, a pair of bit lines forming each column in the memory array to a voltage level of the primary voltage;
• enabling a pair of word lines in the plural rows of the memory array;
• selecting one column of the plural columns in the memory array, wherein a pair of memory cells in the selected column are activated based on the enabled pair of word lines;
• comparing the pair of bit lines for the pair of activated memory cells for the selected column;
• enabling the sense amplifier connected to the pair of bit lines forming the selected column;
• reading a latched bit value at an output terminal of the sense amplifier;
• and
• determining whether latched bit value is consistent with a predefined bit values written to the pair of activated memory cells based on the binary value output by the sense amplifier.