Sram-based in-memory computing macro using analog computation scheme

An in-memory computing array comprising:

• a bit line region;
• a word line region;
• an input and output region;
• and
• a plurality of multiply-and-accumulate (MAC) computational units forming a MAC array, wherein:
• a MAC computational unit includes a plurality of multi-bit multi-bank clusters wherein outputs of at least two multi-bit multi-bank clusters are electrically coupled to an output analog activation line;
• a multi-bit multi-bank cluster includes a C-2C ladder electrically coupled to an input analog activation line and a plurality of single-bit multi-bank clusters stacked to form the multi-bit multi-bank cluster;
• a single-bit multi-bank cluster comprising a part of the C-2C ladder and a plurality of static random access memory (SRAM) cells;
• and
• one or more of the bit line region, the word line region, and the input and output region are located at grid locations associated with a compiled SRAM macro generated before an inclusion of the C-2C ladder.

One or more non-transitory computer readable storage media storing instructions, that when executed by a processor, cause a processor to:

• receive a compiled static random access memory (SRAM) macro generated based on a size of an in-memory compute array, the compiled SRAM macro having a plurality of SRAM cell clusters, a bit line region, and a word line region;
• form a single-bit multi-bank cell cluster from a SRAM cell cluster by:
• removing a plurality of SRAM cells at a location of the SRAM cell cluster in the compiled SRAM macro;
• adding a plurality of further SRAM cells at the location;
• removing one or more yet further SRAM cells at a further location of the SRAM cell cluster of the compiled SRAM macro;
• and
• adding a portion of a C-2C ladder at the further location;
• form a multi-bit multi-bank cell cluster by duplicating the single-bit multi-bank cell cluster;
• form a multiply-and-accumulate (MAC) computational unit by duplicating the multi-bit multi-bank cell cluster;
• and
• form a MAC array by duplicating the MAC computational unit.

A method for generating a static random access memory (SRAM) based in-memory computing macro, the method comprising:

• receiving a compiled static random access memory (SRAM) macro generated based on a size of an in-memory compute array, the compiled SRAM macro having a plurality of SRAM cell clusters, a bit line region, and a word line region;
• forming a single-bit multi-bank cell cluster from a SRAM cell cluster by:
• removing a plurality of SRAM cells at a location of the SRAM cell cluster in the compiled SRAM macro;
• adding a plurality of further SRAM cells at the location;
• removing one or more yet further SRAM cells at a further location of the SRAM cell cluster of the compiled SRAM macro;
• and
• adding a portion of a C-2C ladder at the further location;
• forming a multi-bit multi-bank cell cluster by duplicating the single-bit multi-bank cell cluster;
• forming a multiply-and-accumulate (MAC) computational unit by duplicating the multi-bit multi-bank cell cluster;
• and
• forming a MAC array by duplicating the MAC computational unit.