Write duty cycle calibration on a memory device

A memory device comprising:

• an array of memory cells;
• a first circuit to generate a voltage level associated with a selected digital data input signal of a set of digital data input signals, wherein the selected digital data input signal corresponds to a write operation associated with one or more memory cells of the array of memory cells;
• a second circuit to compare the voltage level to a reference voltage level to generate a comparison result;
• and
• control logic operatively coupled to the second circuit, the control logic to:
• receive a duty cycle calibration command from a memory sub-system controller, the duty cycle calibration command identifying the selected digital data input signal from the set of digital data input signals;
• and
• generate, based on the comparison result, a command comprising a code to adjust a duty cycle associated with the selected digital data input signal.

A memory device comprising:

• an array of memory cells;
• control logic operatively coupled to the array of memory cells, the control logic to:
• identify a duty cycle distortion level associated with a selected digital data input signal of a plurality of digital data input signals;
• and
• generate, based on the duty cycle distortion level, a command comprising a code to adjust a duty cycle associated with the selected digital data input signal;
• and
• a duty cycle adjustment component operatively coupled to the control logic, the duty cycle adjustment component configured to:
• receive the command from the control logic;
• and
• adjust the duty cycle associated with the selected digital data input signal based on the code.