Apparatus for data read timing calibration in stacked memory

An apparatus, comprising:

• a plurality of through-silicon vias (TSVs);
• a plurality of core dies stacked with one another, each core die configured to output read data to one or more assigned TSVs of the plurality of TSVs in response to a read enable signal;
• and
• a calibration circuit configured to:
• compare data read timings of the core dies to determine a slowest core die;
• and
• add a delay to the read enable signal of at least one of the core dies other than the slowest core die to cause the data read timing of the at least one of the core dies match the data read timing of the slowest core die, wherein
• the calibration circuit includes:
• a plurality of first flip-flop circuits configured to receive the read data from corresponding core dies of the plurality of core dies as first data signals, receive the read data from at least one core die selected from the plurality of core dies as a first clock signal, and output first calibration control signals;
• and
• a second flip-flop circuit configured to receive the first calibration control signals as a second data signal, receive a second clock signal, and output a second calibration control signal to indicate the slowest core die, and
• if all of the first calibration control signals output from the first flip-flop circuits are in a high state, the second calibration control signal from the second flip-flop circuit indicates that the selected core die is the slowest core die.

An apparatus, comprising:

• a plurality of through-silicon vias (TSVs);
• a plurality of core dies stacked with one another, each core die configured to output read data to one or more assigned TSVs of the plurality of TSVs in response to a read enable signal;
• and
• a calibration circuit configured to:
• compare data read timings of the core dies to determine a slowest core die;
• and
• add a delay to the read enable signal of at least one of the core dies other than the slowest core die to cause the data read timing of the at least one of the core dies match the data read timing of the slowest core die, wherein
• the at least one of the core dies other than the slowest core die is a calibration-target core die, and
• the calibration circuit includes:
• a phase detecting circuit configured to receive the read data from the slowest core die as a data signal, receive the read data from the calibration-target core die as a clock signal, and output a phase detection result;
• and
• a delay adding circuit configured to calibrate an amount of the delay in response to the phase detection result and a delay amount control signal, the delay amount control signal changing a value thereof at every calibration timing, and to add the delay of the calibrated amount to the read enable signal of the calibration-target core die.