US 2026/0100217 A1 · CLOCK SIGNAL GATING CIRCUIT

Abstract

A clock signal gating circuit including a clock signal input buffer, a first logic circuit, a second logic circuit, and a latch circuit is provided. The clock signal input buffer receives a clock signal and outputs an internal clock signal based on a clock switch signal. The first logic circuit receives an asynchronous clock enable signal and a synchronous clock enable signal and outputs the clock switch signal. The second logic circuit receives the asynchronous clock enable signal, the synchronous clock enable signal, and the internal clock signal and outputs a clock gating signal. The latch circuit receives the asynchronous clock enable signal and the clock gating signal to output the synchronous clock enable signal.

Claims15

Dependent claims

A clock signal gating circuit, comprising:

a clock signal input buffer, receiving a clock signal and outputting an internal clock signal based on a clock switch signal;
a first logic circuit, receiving an asynchronous clock enable signal and a synchronous clock enable signal and outputting the clock switch signal;
a second logic circuit, receiving the asynchronous clock enable signal, the synchronous clock enable signal, and the internal clock signal and outputting a clock gating signal;
and
a latch circuit, receiving the asynchronous clock enable signal and the clock gating signal to output the synchronous clock enable signal.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/333,336Filed 18 Sep 2025

Priority

TW 1131385069 Oct 2024

Published

9 Apr 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 11/4076
For memory cells of the field-effect type: timing circuits
H03K 3/037
By the use of logic circuits, with internal or external positive feedback: bistable circuits
H03K 5/135
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: by the use of time reference…
H03K 19/21
Characterised by logic function, e.g. AND, OR, NOR, NOT circuits: eXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one…

Clock signal gating circuit

Life of this patent

Clock signal gating circuit

Life of this patent

Abstract

Claims15