Dynamic random-access memory (dram) device

A dynamic random-access memory (DRAM) device, comprising:

• at least one slave DRAM chip, wherein each of the at least one slave DRAM chip comprises:
• a slave control circuit, configured to generate a slave control signal according to a slave category signal and a setting signal;
• and
• a slave power circuit, coupled to the slave control circuit and configured to stop generating at least one of a plurality of slave voltages in response to a first value of the slave control signal and generate the plurality of slave voltages in response to a second value of the slave control signal;
• and
• a master DRAM chip, coupled to the at least one slave DRAM chip and configured to control an operation of the at least one slave DRAM chip, wherein the master DRAM chip comprises:
• a master control circuit, configured to generate a master control signal according to a master category signal and the setting signal, and to control the master DRAM chip to generate a plurality of master voltages according to the master control signal,
• wherein the slave category signal is different from the master category signal.