Dual-port memory circuit comprising feram cells

A method for making a dual-access memory circuit, comprising at least:

• providing memory cells of the FeRAM type arranged in rows and columns, each memory cell comprising at least one memory element a first electrode of which is coupled to a plate line common to a column of memory cells, and at least one first and one second access transistors, each coupled to one of first and second bit lines common to said column of memory cells and having a gate coupled to one of first and second word lines common to a row of memory cells;
• providing sense amplifiers and write drive circuits;
• providing interconnection circuits each configured to couple the first and second bit lines and the plate lines of at least one column of memory cells to one of the write drive circuits and to at least one of the sense amplifiers;
• wherein, during a dual read and/or write access to selected first and second memory cells belonging to different columns of memory cells and different rows of memory cells, the memory circuit is configured to apply, to bit lines coupled to access transistors set to the on state and of other memory cells belonging to the same columns of memory cells than the selected first and second memory cells, electrical potentials of the same values as those applied to the plate lines coupled to the memory elements of the selected first and second memory cells, and
• wherein, during a dual read and/or write access to first and second selected memory cells, the memory circuit is configured to apply, to the bit lines coupled to the access transistors set in the on state and of unselected memory cells belonging to columns other than those to which the first and second selected memory cells belong, electrical potentials of the same values as those applied to the plate lines coupled to the memory elements of these unselected memory cells.

A method for controlling memory cells of a memory circuit comprising at least:

• memory cells of the FeRAM type arranged in rows and columns, each memory cell comprising at least one memory element a first electrode of which is coupled to a plate line common to a column of memory cells, and at least one first and one second access transistors each coupled to one of first and second bit lines common to said column of memory cells and having a gate coupled to one of first and second word lines common to a row of memory cells;
• sense amplifiers and write drive circuits;
• interconnection circuits each configured to couple the first and second bit lines and the plate lines of at least one column of memory cells to one of the write drive circuits and to at least one of the sense amplifiers;
• and wherein, during a dual read and/or write access to first and second selected memory cells belonging to different columns of memory cells and different rows of memory cells, the method comprises applying, to bit lines coupled to access transistors set to the on state and of other memory cells belonging to the same columns of memory cells than the first and second selected memory cells, electrical potentials of the same values as those applied to the plate lines coupled to the memory elements of the first and second selected memory cells, and
• wherein, during a dual read and/or write access to first and second selected memory cells, the method comprises applying, to the bit lines coupled to the access transistors set in the on state and of unselected memory cells belonging to columns other than those to which the first and second selected memory cells belong, electrical potentials of the same values as those applied to the plate lines coupled to the memory elements of these unselected memory cells.