Data storage device and memory controller with reduced internal signal transmission delay

Abstract

A data storage device includes a memory device and a host interface. The host interface, communicates with a host device and includes a first circuit and a second circuit. The first circuit is configured on a signal reception path and operates in a first power domain. The first circuit receives a plurality of signals from the host device, and the signals comprise a clock signal provided by the host device. The second circuit is configured on a signal transmission path and operates in the first power domain. The second circuit outputs data read from the memory device according to the clock signal. The first circuit is coupled to the second circuit and the clock signal is directly provided from the first circuit to the second circuit.

Dependencies are inferred from the claim text.