Semiconductor memory devices with embedded power structure and methods of manufacturing thereof

A semiconductor device, comprising:

• a first active region formed at a first level on a first side of a substrate and extending along a first lateral direction;
• a second active region formed at the first level and extending along the first lateral direction;
• a first gate structure formed at the first level, extending in a second lateral direction, and traversing the first and second active regions;
• a second gate structure formed at the first level, extending in the second lateral direction, and traversing the first and second active regions;
• a third active region formed at a second level over the first level on the first side, extending in the first lateral direction, and vertically above and aligned with the first active region;
• a fourth active region formed at the second level, extending in the first lateral direction, and vertically above and aligned with the second active region;
• a third gate structure formed at the second level, extending in the second lateral direction, and vertically above and aligned with the third active region;
• a fourth gate structure formed at the second level, extending in the second lateral direction, and vertically above and aligned with the fourth active region;
• and
• a power structure vertically extending from the first level to the second level, interposed between the first active region and the second active region along the second lateral direction, and interposed between the third active region and the fourth active region along the second lateral direction;
• wherein the first active region and the second gate structure operatively form a first transistor of a memory cell that has a first conductivity, the second active region and the first gate structure operatively form a second transistor of the memory cell that has the first conductivity, the third active region and the third gate structure operatively form a third transistor of the memory cell that have a second conductivity, the third active region and the fourth gate structure operatively form a fourth transistor of the memory cell that have the second conductivity, the fourth active region and the third gate structure operatively form a fifth transistor of the memory cell that have the second conductivity, and the fourth active region and the fourth gate structure operatively form a sixth transistor of the memory cell that have the second conductivity.

A method for forming a memory device, comprising:

• forming, at a first level on a first side of a substrate, a first active region extending along a first lateral direction;
• forming, at the first level, a second active region extending along the first lateral direction;
• forming, at the first level, a first gate structure extending along a second lateral direction and traversing the first and second active regions;
• forming, at the first level, a second gate structure extending along the second lateral direction and traversing the first and second active regions;
• forming, at a second level over the first level on the first side, a third active region extending in the first lateral direction;
• forming, at the second level, a fourth active region extending along the first lateral direction;
• forming, at the second level, a third gate structure extending along the second lateral direction;
• forming, at the second level, a fourth gate structure extending along the second lateral direction;
• and
• forming a power structure vertically extending from the first level to the second level, interposed between the first active region and the second active region along the second lateral direction, and interposed between the third active region and the fourth active region along the second lateral direction;
• wherein the first active region and the second gate structure operatively form a first transistor of a memory cell that has a first conductivity, the second active region and the first gate structure operatively form a second transistor of the memory cell that has the first conductivity, the third active region and the third gate structure operatively form a third transistor of the memory cell that have a second conductivity, the third active region and the fourth gate structure operatively form a fourth transistor of the memory cell that have the second conductivity, the fourth active region and the third gate structure operatively form a fifth transistor of the memory cell that have the second conductivity, and the fourth active region and the fourth gate structure operatively form a sixth transistor of the memory cell that have the second conductivity.