Scan driver, display device, and electronic device including the same

A display device comprising:

• a plurality of pixels in a display area of a display panel;
• a touch sensing unit on a front of the display panel and integrally formed with the display panel;
• a display driver configured to control data voltages supplied to the pixels and image display timing of the pixels;
• and
• a scan driver configured to sequentially drive scan signal lines connected to the pixels based on gate control signals input from the display driver,
• wherein the scan driver comprises:
• a plurality of signal pads configured to receive the gate control signals;
• a phase inversion circuit unit configured to invert a phase of at least one gate control signal based on at least one other gate control signal among the gate control signals and to output the gate control signal having an inverted phase as an output timing signal;
• and
• stage circuits configured to sequentially output scan signals to the scan signal lines based on the output timing signal and the gate control signals.

An electronic device comprising:

• a processor;
• a memory connected to the processor;
• and
• a display device connected to the processor,
• wherein the display device comprising:
• a plurality of pixels in a display area of a display panel;
• a touch sensing unit on a front of the display panel and integrally formed with the display panel;
• a display driver configured to control data voltages supplied to the pixels and image display timing of the pixels;
• and
• a scan driver configured to sequentially drive scan signal lines connected to the pixels based on gate control signals input from the display driver,
• wherein the scan driver comprises:
• a plurality of signal pads configured to receive the gate control signals;
• a phase inversion circuit unit configured to invert a phase of at least one gate control signal based on at least one other gate control signal among the gate control signals and to output the gate control signal having an inverted phase as an output timing signal;
• and
• stage circuits configured to sequentially output scan signals to the scan signal lines based on the output timing signal and the gate control signals.