Electronic design automation machine learning graph representation learning framework for digital ic design automation

Abstract

A framework and associated data schema is used for machine learning-based prediction of performance metrics in digital integrated circuit (IC) design. In one aspect, a computer-implemented method converts design data from an initial design stage into one or more graph representations comprising nodes and edges, each annotated with structural, spatial, and performance-related features. A graph neural network, selected from a graph convolutional neural network (GCN), a spatial graph convolutional neural network (SGCN), or a hybrid thereof, processes the graph to generate embeddings for predicting one or more downstream performance metrics, including arrival time, interconnect parasitic impedance, total power, total area, or slack violations. Graph types include netlist, timing path, interconnect, clock network, and fused multi-graph representations. The method supports multi-stage and iterative predictions, feature importance analysis, ensemble models, and composite loss functions.

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