Efficient management of queue entry state

A system comprising:

• a memory storing a queue and a data structure associated with the queue, wherein the queue comprises a plurality of segments and the data structure associated with the queue comprises a plurality of sections, and wherein each section comprises one or more counters each associated with a segment of the plurality of segments;
• and
• processing circuitry coupled to the memory, the processing circuitry to:
• provide a first entry of the queue to a first process;
• provide a second entry of the queue to a second process;
• responsive to receiving a first signal from the first process, modify the data structure associated with the queue for the first entry, wherein to modify the data structure for the first entry the processing circuitry is to increment a first counter;
• responsive to receiving a second signal from the second process, modify the data structure associated with the queue for the second entry, wherein to modify the data structure for the second entry the processing circuitry is to increment a second counter;
• and
• modify a tail pointer of the queue based on the data structure associated with the queue.

A system comprising:

• a first processor;
• a second processor;
• and
• processing circuitry coupled to the first processor and the second processor, the processing circuitry to:
• provide a first entry of a queue to the first processor, wherein the queue comprises a plurality of segments;
• provide a second entry of the queue to the second processor;
• responsive to receiving a first signal from the first processor, modify a data structure associated with the queue for the first entry, wherein the data structure associated with the queue comprises a plurality of sections, wherein each section comprises one or more counters each associated with a segment of the plurality of segments, and wherein to modify the data structure associated with the queue for the first entry, the processing circuitry is to increment a first counter;
• responsive to receiving a second signal from the second processor, modify the data structure associated with the queue for the second entry, wherein to modify the data structure associated with the queue for the second entry, the processing circuitry is to increment a second counter;
• and
• modify a tail pointer of the queue based on the data structure associated with the queue.