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AssigneeQUALCOMM Incorporated
InventorsDinesh Kumar Choudhary, Sai Sneha Venkata Yesantarao, Raja Simha Revanuru
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A system-on-chip (SoC) performance management technique is described for designs with multiple clock domains sharing a power supply. The technique involves a shared rail boost (SRB) feature that adjusts performance states across different clock domains. The SRB feature is enabled based on conditions such as utilization levels, active core counts, or voltage differences between domains. When enabled, the SRB feature allows assignment of a higher performance state to a clock domain. The technique compares open-loop voltages between domains and aggregates target and recommended performance states to determine final states. It includes mechanisms for disabling the SRB feature under certain conditions and considers the performance states of other clock domains. The approach operates independently of schedulers or kernels, allowing for integration into various SoC designs.
A method for managing performance in a system-on-chip (SoC) having multiple clock domains, the method comprising:
An apparatus for managing performance in a system-on-chip (SoC) having multiple clock domains, comprising:
An apparatus for managing performance in a system-on-chip (SoC) having more than one clock domains, comprising:
Dependencies are inferred from the claim text.