US 2026/0099439 A1 · Clock phase control circuits and electronic device

Abstract

A clock phase control circuit includes a sampling circuit and a phase monitoring circuit. The sampling circuit receives a plurality of reference clock signals and, in response to a read command, samples data read from a memory device according to the reference clock signals to obtain a plurality of sampling results. The reference clock signals are generated based on a fundamental clock signal with different candidate phases. The phase monitoring circuit receives the sampling results and determines an optimal phase according to the sampling results. The data read from the memory device comprises data in one or more data blocks which are sequentially received in response to the read command. In response to an end of each data block, a sampling phase of the fundamental clock signal to sample the data read from the memory device is adjusted according to the optimal phase.

Claims17

Dependent claims

A clock phase control circuit, comprising:

a sampling circuit, receiving a plurality of reference clock signals and, in response to a read command, sampling data read from a memory device according to the reference clock signals to obtain a plurality of sampling results, wherein the reference clock signals are generated based on a fundamental clock signal with different candidate phases;
and
a phase monitoring circuit, receiving the sampling results and determining an optimal phase according to the sampling results,
wherein the data read from the memory device comprises data in one or more data blocks which are sequentially received in response to the read command, and
wherein in response to an end of each data block, a sampling phase of the fundamental clock signal to sample the data read from the memory device is adjusted according to the optimal phase.

2 more elements

An electronic device, coupled to a data storage device, comprising:

a receiving circuit, receiving data read from a memory device of the data storage device;
and
a signal processing circuit, processing the data read from the memory device, wherein the data comprises data in one or more data blocks which are sequentially received in response to a read command, and wherein the signal processing circuit comprises:
a clock signal generating circuit, generating a plurality of reference clock signals based on a fundamental clock signal with different candidate phases, wherein the candidate phases comprise a sampling phase of the fundamental clock signal currently set to sample the data;
and
a clock phase control circuit, repeatedly determining an optimal phase according to a plurality of sampling results obtained according to the reference clock signals and providing information regarding the optimal phase to the clock signal generating circuit to adjust the sampling phase of the fundamental clock signal in response to an end of each data block.

3 more elements

Dependencies are inferred from the claim text.

Clock phase control circuits and electronic device

Life of this patent

Clock phase control circuits and electronic device

Life of this patent

Abstract

Claims17