Error correction

An error correction apparatus, comprising

• a memory,
• a code circuit arrangement configured to
• read a bit group of n memory cells from the memory,
• determine n states based on the read bit group, wherein the n states are determined in a time domain for a k1-out-of-n code and for a k2-out-of-n code, where k1 is less than k2,
• use a previously read n-bit code word of the k1-out-of-n code for a read n-bit word, which is a non-code word instead of a code word of the k2-out-of-n code, to determine possible erroneous bits in the non-code word,
• determine possible code words of the k2-out-of-n code for the non-code word based on the possible erroneous bits,
• perform error correction using an external error code based on the possible code words.

An apparatus, comprising:

• a plurality of memory cells;
• a plurality of sense amplifiers having a plurality of inputs, respectively, and a plurality of outputs, respectively;
• the plurality of inputs of the sense amplifiers coupled to a plurality of outputs of the memory cells, respectively;
• a plurality of latches each having a first input, a second input, and an output;
• the first inputs of the plurality of latches respectively coupled to the plurality of outputs of the sense amplifiers;
• and
• a circuit block having a plurality of inputs and an output, the plurality of inputs of the circuit block respectively coupled to the outputs of the plurality of latches, and the output of the circuit block coupled to the second inputs of the plurality of latches.