Reducing DRAM Utilization For Error Correction Codes While Maintaining Error Detection And Correction

Abstract

The technology is directed to error detection and correction in a memory device containing dynamic random-access memory (DRAM) elements. The DRAM elements are configured to store data in a first number of elements, store error correction code (ECC) information in a second number of elements and storing an error correction code in a third number of elements. The amount of memory allocated to ECC is reduced without adversely affecting the ECC capability by storing an error correction code, such as a cyclic redundancy code (CRC) in the freed-up memory space. A location of an uncorrectable error is identified assuming one of the elements contains an error then recalculating the selected data using the ECC, recalculating the CRC and comparing it to the original CRC. A match indicates the faulty value has been found and corrected. A mismatch indicates that the selected element is not the location of the error.

Dependencies are inferred from the claim text.