US 2026/0099331 A1 · OPERAND-LESS INSTRUCTION SET ARCHITECTURE-BASED PROCESSOR AND COMPUTER HAVING THE SAME

Abstract

It is disclosed that to an operand-less instruction set architecture-based processor and a computer having the operand-less instruction set architecture-based processor. An operand-less instruction set architecture-based processor includes an instruction processing unit configured to process program instructions that do not require operands, except for instructions related to receiving and transmitting data; one or more functional processing units configured to perform a plurality of functions for data processing; and a stacked register configured to separate instruction processing by the instruction processing unit from data processing by the functional processing unit.

Claims20

Dependent claims

An operand-less instruction set architecture-based processor comprising:

an instruction processing unit configured to process program instructions that do not require operands, except for instructions related to receiving and transmitting data;
one or more functional processing units configured to perform a plurality of functions for data processing;
and
a stacked register configured to separate instruction processing by the instruction processing unit from data processing by the functional processing unit.

1 more element

An operand-less instruction set architecture-based computer comprising:

an instruction memory configured to store the instructions of the program;
a data memory configured to store data necessary for the execution of the program;
and
a processor configured to read the program instructions from the instruction memory and to receive and transmit data from the data memory, wherein the processor comprises:
an instruction processing unit configured to process program instructions, but having no operand other than instructions for receiving and transmitting data;
one or more functional processing units configured to perform a plurality of functions for data processing;
and
a stacked register configured to separate instruction processing by the instruction processing unit from data processing by the functional processing unit.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/966,326Filed 3 Dec 2024

Priority

KR 10-2024-01366558 Oct 2024

Published

9 Apr 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 9/3802
Concurrent instruction execution, e.g. pipeline or look ahead: instruction prefetching
G06F 9/3001
To perform operations on data operands: arithmetic instructions
G06F 9/3016
Instruction analysis, e.g. decoding, instruction word fields: decoding the operand specifier, e.g. specifier format
G06F 9/321
Address formation of the next instruction, e.g. by incrementing the instruction counter: program or instruction counter, e.g. incrementing

Operand-less instruction set architecture-based processor and computer having the same

Life of this patent

Operand-less instruction set architecture-based processor and computer having the same

Life of this patent

Abstract

Claims20