Vector processor performance enhancement
AssigneeMicrosemi SoC Corporation
InventorsArunkumar Devidas Naik, Aaron Severance
Life of this patent
Estimating the term…
Abstract
The system may speed up reduced instruction set computing/single instruction, multiple data (RISCV/SIMD) vector processing (VP) by adding a register circuit for an additional vector register file for a total of two VRF registers. One of the VRF registers may be used for data transfers to and from memory, and the other VRF register may be used for arithmetic logic unit (ALU) operands. The VRFs may be switched alternatively to perform the data transfers and operands.
Claims21
A vector processor system, comprising:
- a vector processor, in a loop iteration cycle, operable to:
- enable a first vector register file to perform a first role of loading vector data of a subsequent loop iteration cycle from a memory into the first vector register file;
- enable a second vector register file to perform a second role of providing input and output registers as operations for an arithmetic logic unit (ALU) operation using vector data of the current loop iteration cycle from the second vector register file;
- enable the first vector register file to further perform the first role of storing a result of an ALU operation using vector data of a prior loop iteration cycle in the first vector register file;
- and
- switch roles of the first vector register file and the second vector register file.
A method of operating a vector processor, comprising:
- enabling a first vector register file to perform a first role of loading vector data from a memory into the first vector register file;
- enabling a second vector register file to perform a second role of performing an arithmetic logic unit (ALU) operation using the vector data from the second vector register file;
- enabling the first vector register file to further perform the first role of storing a result of the ALU operation in the first vector register file;
- and
- switching roles of the first vector register file and the second vector register file.
A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations comprising:
- enabling a first vector register file and a second vector register file in a vector processor;
- alternately using the first vector register file for memory operations and the second vector register file for arithmetic logic unit (ALU) operations;
- and
- switching roles of the first vector register file and the second vector register file after completing a set of vector operations.
Dependencies are inferred from the claim text.