Adaptive Host Memory Buffer Traffic Control

A data storage device, comprising:

• a memory device;
• and
• a controller coupled to the memory device, wherein the controller comprises:
• a host memory buffer latency control module, wherein the host memory buffer latency control module is configured to:
• track a turnaround latency to complete a request directed towards another memory device, wherein the another memory device is external to the data storage device;
• determine whether the turnaround latency is greater than or equal to a threshold latency;
• and
• set an indication to read from the memory device or the another memory device for a same data stored in both the memory device and the another memory device based on the determining, wherein the threshold latency is based on an expected read time for the memory device and an availability of a requested data corresponding to the request in the memory device.

A data storage device, comprising:

• memory means;
• and
• a controller coupled to the memory means, wherein the controller is configured to:
• receive a read request from a host device;
• determine that a read address corresponding to the read request exists in both the memory means and an another memory means, wherein the another memory means is disposed in the host device;
• retrieve the read address from either the memory means or the another memory means based on a tracked turnaround latency, wherein the tracked turnaround latency corresponds to a completion latency of one or more previously completed read address retrieval commands;
• retrieve the read address from the another memory means when the another memory means is not full and when the tracked turnaround latency is less than a threshold latency;
• determine that a queue of the another memory means is full;
• and
• send a next request to the another memory means or the memory means based on whether a same data is present in the another memory means and whether the queue of the another memory means is full.

A data storage device, comprising:

• memory means;
• and
• a controller coupled to the memory means, wherein the controller is configured to:
• receive a read request from a host device;
• determine that a read address corresponding to the read request exists in both the memory means and an another memory means, wherein the another memory means is disposed in the host device;
• retrieve the read address from either the memory means or the another memory means based on a tracked turnaround latency, wherein the tracked turnaround latency corresponds to a completion latency of one or more previously completed read address retrieval commands;
• compare the tracked turnaround latency to a threshold latency, wherein the threshold latency is based on:
• an average latency of a number of previous read requests to the another memory means;
• or
• a maximum latency of the number of previous read requests to the another memory means;
• determine that a queue of the another memory means is full;
• and
• send a next request to the another memory means or the memory means based on whether a same data is present in the another memory means and whether the queue of the another memory means is full.