Power voltage phase adjustment for adaptive clock distribution system

A method comprising:

• receiving a clock signal at an adaptive clock distribution circuit, the clock signal having a voltage and a frequency;
• receiving a sensed voltage of the clock signal from one or more active circuits;
• delaying the sensed voltage at a filter circuit to provide a tuned sensed voltage;
• detecting a voltage drop of the tuned sensed voltage;
• reducing the frequency of the clock signal in response to the detecting the voltage droop;
• and
• providing the clock signal to the one or more active circuits to drive the one or more active circuits at the voltage and the frequency.

A computing system comprising:

• an integrated circuit having at least one core, the core including one or more active circuits;
• a clock signal source configured to generate a clock signal for the one or more active circuits of the core, the clock signal having a voltage and a frequency;
• a voltage distribution circuit coupled to the clock signal source configured to distribute the clock signal to the core;
• a filter circuit coupled to the one or more active circuits to receive a sensed voltage of the clock signal from the one or more active circuits and configured to delay the sensed voltage to provide a tuned sensed voltage;
• and
• an adaptive clock distribution circuit coupled to the clock signal source to receive the clock signal and coupled to the voltage distribution circuit to provide the clock signal to the one or more active circuits, the adaptive clock distribution circuit coupled to the filter circuit to receive the tuned sensed voltage from the filter circuit, and configured to detect a voltage drop of the tuned sensed voltage with respect to the clock signal, and to reduce the frequency for the one or more active circuits in response to the voltage droop.