Time-to-digital conversion device

A method of generating a count value indicative of a time difference between a first event and a second event, comprising:

• outputting, by a first oscillator, a first clock signal in response to the first event, the first clock signal having a first clock period;
• outputting, by a second oscillator, a second clock signal in response to the second event, the second clock signal having a second clock period, the first event occurring before the second event, and the first clock period being greater than the second clock period;
• generating, by a phase detector, a detection signal based on a phase relationship between the first clock signal and the second clock signal;
• and
• generating, by a clock counter, the count value based on the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal.

An integrated circuit die, comprising:

• one or more digital circuit blocks configured to output a first reference signal and a second reference signal;
• and
• a time-to-digital conversion device configured to output a count value indicative of a time difference between a first event and a second event, the time-to-digital conversion device comprising:
• a first oscillator configured to output a first clock signal in response to the first event based on the first reference signal, the first clock signal having a first clock period;
• a second oscillator configured to output a second clock signal in response to the second event based on the second reference signal, the second clock signal having a second clock period, the first event occurring before the second event, and the first clock period being greater than the second clock period;
• a phase detector configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal;
• and
• a clock counter configured to generate a count value based on the first clock signal in response to the detection signal indicating that a phase of the second clock signal lags behind a phase of the first clock signal.