Semiconductor package

A semiconductor package, comprising:

• a first semiconductor chip including a first substrate and a first wiring layer on the first substrate;
• a second semiconductor chip including a first chiplet die mounted on the first semiconductor chip via a plurality of first conductive connection members, a second chiplet die mounted on the first semiconductor chip via a plurality of second conductive connection members, and a third chiplet die mounted on the first semiconductor chip via a plurality of third conductive connection members, wherein the first chiplet die, the second chiplet die, and the third chiplet die are spaced apart from each other in a first horizontal direction to define a first gap between the first chiplet die and the second chiplet die and to define a second gap between the second chiplet die and the third chiplet die;
• and
• a molding member on the first semiconductor chip and covering the first chiplet die, the second chiplet die, and the third chiplet die,
• wherein a distance in a vertical direction between a lower surface of the first substrate and a highest one of an upper surface of the first chiplet die, an upper surface of the second chiplet die and an upper surface of the third chiplet die has a first height,
• wherein the plurality of first conductive connection members, the plurality of second conductive connection members, and the plurality of third conductive connection members are below a central extension line passing through a center of the first height,
• wherein a coefficient of thermal expansion of the molding member is greater than a coefficient of thermal expansion of the first semiconductor chip,
• wherein a first extension portion of the molding member fills the first gap, and
• wherein a second extension portion of the molding member fills the second gap.

A semiconductor package, comprising:

• a first semiconductor chip;
• at least one chiplet die mounted on the first semiconductor chip;
• a first chip structure on the first semiconductor chip, the first chip structure being spaced apart from the at least one chiplet die in a first horizontal direction to define a first gap between the first chip structure and the at least one chiplet die;
• a second chip structure on the first semiconductor chip, the second chip structure being spaced apart from the at least one chiplet die and the first chip structure in the first horizontal direction to define a second gap between the second chip structure and the first chip structure;
• and
• a molding member on the first semiconductor chip and covering the at least one chiplet die, the first chip structure, and the second chip structure,
• wherein a thickness of at least one of the at least one chiplet die, the first chip structure, and the second chip structure is greater than a thickness of the first semiconductor chip;
• wherein a coefficient of thermal expansion of the molding member is greater than a coefficient of thermal expansion of the first semiconductor chip,
• wherein a first extension portion of the molding member fills the first gap, and
• wherein a second extension portion of the molding member fills the second gap.