Semiconductor package and manufacturing method thereof

A semiconductor package comprising:

• a first redistribution structure;
• a logic die on the first redistribution structure;
• a plurality of conductive posts on the first redistribution structure, the plurality of conductive posts being laterally next to the logic die;
• a second redistribution structure on the logic die and the plurality of conductive posts;
• and
• a memory package on the second redistribution structure,
• wherein the memory package includes
• a plurality of bumps,
• an interposer on the plurality of bumps,
• a heat dissipating structure on the interposer, and
• a memory structure on the interposer, the memory structure being laterally next to the heat dissipating structure.

A semiconductor package comprising:

• a front-side redistribution structure;
• a logic die on the front-side redistribution structure;
• conductive posts on the front-side redistribution structure, the conductive posts being laterally next to the logic die;
• a first molding material covering the logic die and the conductive posts on the front-side redistribution structure;
• a back-side redistribution structure on the conductive posts and the first molding material;
• a memory package on the back-side redistribution structure;
• and
• a second molding material covering the memory package on the back-side redistribution structure,
• wherein the memory package includes
• an interposer defining a through opening through the interposer,
• a plurality of first bumps between the back-side redistribution structure and the interposer,
• a heat dissipating structure in the through opening,
• a plurality of second bumps between the back-side redistribution structure and the heat dissipating structure,
• a memory structure on the interposer, the memory structure being laterally next to the heat dissipating structure, and
• a third molding material covering the memory structure on the interposer.