Semiconductor devices

A semiconductor device, comprising:

• a lower interlayer insulating film;
• a lower bonding pad in the lower interlayer insulating film;
• a lower alignment pattern in the lower interlayer insulating film, wherein the lower alignment pattern is spaced apart from the lower bonding pad in a horizontal direction that is parallel with an upper surface and/or a lower surface of the lower interlayer insulating film;
• an upper interlayer insulating film on the lower interlayer insulating film;
• an upper bonding pad in the upper interlayer insulating film, wherein the upper bonding pad is in contact with the lower bonding pad;
• and
• an upper alignment pattern in the upper interlayer insulating film, wherein the upper alignment pattern is spaced apart from the upper bonding pad in the horizontal direction,
• wherein the lower alignment pattern comprises sub-lower alignment patterns, and
• wherein a width of at least one of the sub-lower alignment patterns in a direction is 10% to 300% of a width of the lower bonding pad in the direction.

A semiconductor device, comprising:

• a substrate that comprises a first region and a second region that is adjacent the first region;
• a peripheral circuit structure on the first region;
• a cell structure on the peripheral circuit structure;
• and
• a lower alignment pattern and an upper alignment pattern on the second region of the substrate, wherein the cell structure comprises:
• gate electrodes that are stacked on and spaced apart from each other in a first direction that is perpendicular to an upper surface and/or a lower surface of the substrate;
• a channel structure that extends into the gate electrodes in the first direction;
• a bit line that is electrically connected to the channel structure;
• and
• an upper bonding pad that is electrically connected to the bit line,
• the peripheral circuit structure comprises:
• a lower bonding pad that is in contact with the upper bonding pad;
• and
• a peripheral circuit element that is electrically connected to the lower bonding pad,
• wherein the lower alignment pattern comprises sub-lower alignment patterns,
• wherein a width of at least one of the sub-lower alignment patterns in a second direction is 10% to 300% of a width of the lower bonding pad in the second direction, and
• wherein the second direction is parallel with the upper surface and/or the lower surface of the substrate.