Power Grid Architecture

An apparatus, comprising:

• an integrated circuit device having a transistor region above a substrate in a vertical dimension perpendicular to the substrate;
• a core logic region in the transistor region, the core logic region including a plurality of functional circuits positioned in the transistor region;
• a power switch region in the transistor region, the power switch region including a plurality of power switch circuits aligned linearly in a horizontal dimension in the transistor region;
• a first set of one or more metal layers positioned above the transistor region in the vertical dimension;
• a second set of one or more metal layers positioned above the first set of one or more metal layers in the vertical dimension;
• a third set of one or more metal layers positioned above the second set of one or more metal layers in the vertical dimension;
• wherein, above the power switch region in the vertical dimension, the first set of one or more metal layers includes two or more layers of mesh routing, wherein the mesh routing in the first set of one or more metal layers include at least one power route coupled to at least one power switch circuit, the at least one power route receiving an output voltage from the at least one power switch circuit;
• wherein a last metal layer of the first set of one or more metal layers furthest from the transistor region in the vertical dimension includes mesh routing coupled to the at least one power route, the mesh routing in the last metal layer having a path above both the power switch region and the core logic region in the vertical dimension;
• and
• wherein, above the core logic region in the vertical dimension, the first set of one or more metal layers includes two or more layers of pillar routing, the pillar routing including at least one power route coupled to the mesh routing in the last metal layer of the first set of one or more metal layers;
• and
• wherein, above the core logic region in the vertical dimension, a lowest metal layer in the first set of one or more metal layers closest to the transistor region in the vertical dimension includes mesh routing, the mesh routing in the lowest metal layer coupling the at least one power route in the two or more layers of pillar routing to at least one functional circuit in the core logic region.

An apparatus, comprising:

• an integrated circuit device having a transistor region above a substrate in a vertical dimension perpendicular to the substrate;
• a core logic region in the transistor region, the core logic region including a plurality of functional circuits positioned in the transistor region;
• a power switch region in the transistor region, the power switch region including a plurality of power switch circuits aligned linearly in a horizontal dimension in the transistor region;
• a first set of one or more metal layers positioned above the transistor region in the vertical dimension;
• a second set of one or more metal layers positioned above the first set of one or more metal layers in the vertical dimension;
• a third set of one or more metal layers positioned above the second set of one or more metal layers in the vertical dimension;
• wherein, above both the core logic region and the power switch region in the vertical dimension, a lowest metal layer in the second set of one or more metal layers closest to the transistor region in the vertical dimension and a last metal layer in the second set of one or more metal layers furthest from the transistor region in the vertical dimension both include mesh routing;
• wherein, above the power switch region in the vertical dimension, the second set of one or more metal layers includes at least two or more metal layers having pillar routing, the at least two metal layers being layers closest to the lowest metal layer in the vertical dimension;
• at least one ground supply route through the first set of one or more metal layers and the second set of one or more metal layers above the core logic region in the vertical dimension, the at least one ground supply route being coupled to at least one functional circuit;
• and
• ground mesh routing in a first metal layer in the third set of one or more metal layers closest to the transistor region in the vertical dimension, the ground mesh routing in the first metal layer being coupled to a power supply circuit and the at least one ground supply route, the ground mesh routing receiving a ground supply voltage from the power supply circuit.