Semiconductor device

A semiconductor device comprising:

• a first channel pattern and a second channel pattern at least partially overlapping;
• a first gate pattern
• between the first channel pattern and the second channel pattern, and
• overlapping the first channel pattern and the second channel pattern;
• a first connection conductive pattern
• spaced apart from the first channel pattern and the second channel pattern, and
• electrically connected to the first gate pattern;
• and
• a source/drain pattern connected to the first channel pattern and the second channel pattern,
• wherein the first channel pattern, the second channel pattern, and the first gate pattern are between an upper surface and a lower surface of the first connection conductive pattern.

A semiconductor device comprising:

• a first channel pattern and a second channel pattern at least partially overlapping;
• a first gate pattern
• between the first channel pattern and the second channel pattern, and
• at least partially overlapping the first channel pattern and the second channel pattern;
• a first connection conductive pattern and a second connection conductive pattern
• spaced apart from each other in a first direction, and
• the first channel pattern, the second channel pattern, and the first gate pattern between the first and second connection conductive patterns;
• a first source/drain pattern connected to the first channel pattern and the second channel pattern;
• a third channel pattern spaced apart from the first channel pattern in the first direction;
• a fourth channel pattern spaced apart from the second channel pattern in the first direction, and overlapping the third channel pattern;
• a second gate pattern
• between the third channel pattern and the fourth channel pattern,
• overlapping the third channel pattern and the fourth channel pattern, and
• spaced apart from the first gate pattern in the first direction;
• a third connection conductive pattern and a fourth connection conductive pattern
• spaced apart from each other in the first direction, and
• the third channel pattern, the fourth channel pattern and the second gate pattern between the third and fourth connection conductive patterns;
• a second source/drain pattern connected to the third channel pattern and the fourth channel pattern;
• a first spacer at least partially overlapping the first and second source/drain patterns;
• a first mask pattern at least partially overlapping the first channel pattern, the second channel pattern, and the first gate pattern;
• a second mask pattern at least partially overlapping the third channel pattern, the fourth channel pattern and the second gate pattern;
• a second spacer on the first and second mask patterns and the first spacer;
• and
• a cover insulating layer on the first and second mask patterns and the first to fourth connection conductive patterns.